The invention is directed to a more efficient approach for hotspot detection, for implementing layout, and for placement, routing, and verification of integrated circuit designs.
A semiconductor integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, wires, etc., that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
The various components of an integrated circuit are initially defined by their functional, operations and relevant inputs and outputs. From the HDL or other high level description, the actual logic cell implementation is typically determined by logic synthesis, which converts the functional description of the circuit into a specific circuit implementation.
An integrated circuit designer may use a set of EDA application programs to create a physical integrated circuit design layout from a logical circuit design. The EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. During this process, the design components are “placed” (i.e., given specific coordinate locations in the circuit layout) and “routed” (i.e., wired or connected together according to the designer's circuit definitions).
After an integrated circuit designer has created the circuit layout, verification and/or optimization operations are performed on the integrated circuit layout using a set of EDA testing and analysis tools. These actions are performed since significant variations from the as-designed IC product may occur to the as-manufactured IC product due to the optical and/or chemical nature of the processing used to manufacture the integrated circuit. For example, optical distortions during the lithography process may cause variations in feature dimensions (e.g. line widths) that are patterned using masks. Physical verification would occur to help identify areas of significant risks for problematic variations. Design optimization approaches, such as OPC (optical proximity correction) and RET (resolution enhancement techniques) could be used to create an as-manufactured product that more closely matches the configuration of the as-designed layout.
The design rule check (DRC) process has long been used to help minimize manufacturing problems, by ensuring that the circuit design abides by a set of detailed rules and parameters that the foundry specifies for its manufacturing process. Essentially, each rule is associated with one or more parameter values that are checked for compliance with the rule. The DRC process will check those parameters to produce a simple “yes” or “no” answer as to whether the rule has been violated. For example, a very common rule is to check for minimum spacing between objects in a layout. DRC processing will determine whether all objects meet the minimum spacing requirements. If all objects meet the spacing requirements, then the layout meet the rules requirement for spacing. If any objects are spaced closer together than the minimum spacing requirement, then a rules violation will be identified, if there are any rules violations, then the layout will need to be modified to correct the rules violation. If no rules violations have been identified, then the IC design is passed to the next design stage for manufacturing.
DRC tools typically read and manipulate a design database which stores information about device geometries and connectivity. Because compliance with design rules generally constitutes the gating factor between one stage of the design and the next, DRC tools are typically executed multiple times during the evolution of the design and contribute significantly to the project's critical path. Therefore, reducing DRC tool execution time makes a major contribution to the reduction of overall design cycle times. In addition, DRC rules often contain design constraints that are much more limiting than are needed for any particular design or portion of a design, DRC rules are often set at the “lowest common denominator” level to ensure that most or all IC designs will properly operate. However, certain IC design may actually need parameters that are more or less cautious than other designs. Since DRC rules typically operate on an “all or nothing” basis, this means that many IC design may fail DRC processing even, though they would function properly for intended purposes if manufactured. Further, manufacturing an IC design has gotten steadily more difficult, so much so that certain 2D configurations of geometry may not function properly, even though they satisfy all the DRC rules.
To address this issue, model-based approaches can be used to verify the circuit design, by using the model to check the design for manufacturing-induced problems. As used herein, the term “model” refers to a set of data that identifies one or more specific characteristics within an IC layout and data relating to its effect, manufacturability, and/or usability. A lithography model is a common example of a type of model that is used by EDA tools during many phases of the electronic design process, such as physical design, implementation, and verification.
FIG. 1 illustrates one approach for performing model-based verification and optimization in the context of routing. This approach begins with a pre-routed design 102 having a set of geometric circuit elements/shapes created with a layout tool. A routing tool would then be used for implementing interconnect elements on the layout to create a routed design 104. The conventional router does not have knowledge of lithography issues. As a result, the routed design may contain numerous layout portions that are problematic once manufacturing is performed, and would contribute to yield or functionality problems.
During the verification/optimization, models (such as lithography models) are used by a lithography simulation device 106 to predict the as-manufactured product that would result from processing the layout in a given manufacturing facility and using a given set of processing equipment and parameters. Optimizations, such as RET optimizations, may also be performed to increase the likelihood of a manufacturable design. If problems are identified, then the design may return for re-routing to correct the identified problems. Numerous iterations of this process may occur before a design is finalized. The term RET (reticle enhancement technology), as used here, includes the use of optical proximity correction (OPC), sub-resolution assist features (SRAF), phase shift masks (PSM), etc.
The problem with this approach is that lithography simulation and RET optimization is very resource intensive, requiring large quantities of both time and computing assets for adequate results. As the quantity of data in modern IC designs become larger and larger over time, the resources required for performing model-based verification and optimization upon these IC designs also becomes much greater. This problem is exacerbated by constantly improving IC manufacturing technologies that can create IC chips at ever-smaller feature sizes, which allows increasingly greater quantities of transistors to be placed within the same chip area, resulting in more complex physical and lithographic effects during manufacture.
To address these problems, among others, the present invention in some embodiments provides an approach for allowing EDA tools to implement very efficient approaches to allow the tools to directly address the effects of manufacturing processes, e.g., to identify and prevent problems caused by lithography processing. Fast models and pattern checking are employed to integrate lithography and manufacturing aware processes within EDA tools such as routers. In some embodiments, this approach avoids the rigid requirement of conventional tools that rely exclusively upon rule checks, avoiding the need to create overly complex rules that may or may not accurately reflect the real-world manufacturing problems that may occur to the design. This also avoids the need to hardcode the EDA fool (e.g., modify the router software) to explicitly target particular bad patterns, which significantly reduces or eliminates the need to perform this highly manual and error-prone effort. Moreover, this approach in some embodiments can also be used to avoid the very slow process of using external tools to verify the routed design and to provide feedback to the router. In this context, the external tool will often call the problems it finds “hotspots”.